ICs should be tested following manufacture to ensure their proper operation. DFT is a design technique that adds testability features to the design of integrated circuits (ICs) to improve the application of manufacturing tests. For this reason, ICs are typically provided with a test access port (TAP) that conforms to Institute of Electrical and Electronics Engineers, Inc., (IEEE) 1149.1, or Joint Test Access Group (JTAG), standard. JTAG specifies a “boundary scanning” technique in which a tester (also called automated test equipment, or ATE) connected to the TAP via a JTAG (serial) bus provides a clock signal and one or more patterns of zeroes and ones (a “test pattern”) to the IC and receives a resulting (“output”) pattern of responses by the IC to the test pattern. An output pattern that does not match expectations indicates a failed test. The output pattern may be analyzed to determine the nature of the IC failure and perhaps where in the IC the failure occurred.
Scan chains are used to test an IC. A scan chain is a connection of flip-flops in an IC that can be configured as a shift register. Scan chains are connected to the ATE via the TAP interface. A scan clock signal driven by the ATE shifts the test data into the scan chains. For any given test block applied by the ATE, the frequency of the scan clock is defined and typically fixed for the duration of the test block. This is the speed at which the test data is shifted into the scan chain. The ATE also drives the TAP and other test control signals for scan testing using the scan chains. A controller of the TAP, a TAP controller, can generate additional test mode signals.
The type of ATE that is used for testing can vary. Though high end testers may have more features, the use of these testers may prove cost prohibitive. Additionally, standard programming tools for ATE may limit the type of variation a tester may desire.